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verilogsystem-verilogverilator

Modify SystemVerilog module parameter value in Verilator simulation (C++)

Is it possible to modify the parameters for a verilated SystemVerilog from a testbench written in C++. For example, consider the module below.

module my_module #(
    parameter WIDTH = 16
)
(
    input logic i_clk, // input clock
    input logic i_rst, // input reset
    output logic [7:0] o_out // output
);

Say I verilate this module, I am able to do the following in C++ after instancing the verilated module:

// Something to the effect of...
VerilatedContext* contextp = new VerilatedContext;
Vmy_module* top = new Vmy_module{contextp};
//...
top->i_rst = 1;

If I wanted to modify the default value for the WIDTH parameter (from within the C++ code), how would I go about doing that?

I've tried marking it public (via /*verilator public*/) to no avail. I have also used the DPI interface to read other internal module signals, however, I'm not sure if they can be applied to write/modify parameters.

Solution

  • You cannot override the value of a parameter at runtime in Verilator. The /*verilator public*/ pragma is for access to a signal from your C++ testbench.

    You can override a parameter before your SystemVerilog code has been translated to C++ using the -G options.