I wrote a code for a bidirectional counter which works as an up counter if parameter updown=1 and down counter otherwise on EDAplayground using icarus verilog as my simulator:
module upctr(
output reg [3:0] num,
input clock
);
always@(posedge clock)
begin
if(num!=4'd9)
num<= num+4'd1;
else
num<= 4'd0;
end
endmodule
module downctr(
output reg [3:0] num,
input clock
);
always@(posedge clock)
begin
if(num!=4'd0)
num<= num-4'd1;
else
num<= 4'd9;
end
endmodule
module testgenerate(
output reg [3:0] result=4'b0000,
input clock
);
parameter updown = 0;
generate
if(updown)
upctr uc(result, clock);
else
downctr dc(result, clock);
endgenerate
endmodule
When I executed the code to troubleshoot it, the following error came:
design.sv:31: error: result Unable to assign to unresolved wires.
Elaboration failed
Exit code expected: 0, received: 1
Can someone please explain what this error means and how do I correct it?
When you don't understand the meaning of error messages, you can try your code on other simulators on edaplayground. With Synopsys VCS, for example:
Error-[ICPSD_INIT] Illegal combination of drivers
Illegal combination of structural and procedural drivers.
Variable "result" is driven by an invalid combination of structural and
procedural drivers. Variables driven by a structural driver cannot have any
other drivers.
This variable is declared at : reg [3:0] result;
The first driver is at : downctr genblk1.dc(result, clock);
The second driver is at : result = 4'b0;
To fix it, change:
output reg [3:0] result=4'b0000,
to:
output [3:0] result,
A more common approach to initializing a counter is to add a separate reset input signal to your design, then drive it from your testbench. There are many examples, such as this one.