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verilogsystem-verilogiverilog

What is ''_'' in Verilog?

I was viewing this code snippet:

module FD2 (d, cp, cd, q, qn);

  input d, cp, cd;
  output q, qn;

  nand #1   nand_2 (n2, d_, cp_),
            nand_3 (n3, n1, n4),
            nand_7 (q, n5, qn);

// SJM  nand #0   nand_1 (n1, d, cp_, cd),
  nand   nand_1 (n1, d, cp_, cd),
            nand_4 (n4, n2, n3, cd),
            nand_5 (n5, n3, cp),
            nand_6 (n6, n4, cp),
            nand_8 (qn, n6, cd, q);

// SJM not  #0   inv_1 (cp_, cp),
  not   inv_1 (cp_, cp),
            inv_2 (d_, d);

endmodule

What does "cp_" signify?

No where I could find answers, so I thought of posting here.

Solution

  • In your code, cp_ is the name of a signal, just like cp is the name of another signal. The underscore has no special meaning in the name. This is an example of a simple identifier. Refer to IEEE Std 1800-2017, section 5.6 Identifiers, keywords, and system names:

    An identifier is used to give an object a unique name so it can be referenced. An identifier is either a simple identifier or an escaped identifier (see 5.6.1). A simple identifier shall be any sequence of letters, digits, dollar signs ( $ ), and underscore characters ( _ ).

    It is legal to not declare signals explicitly, but it is a recommended good practice to do so. It would be better to declare the signal using:

    wire cp_;

    The same is true for other signals which have not been declared, such as d_, n1, etc.

    See also section 6.10 Implicit declarations.