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verilogsystem-verilog

Concatenation in output of module

When I instantiate a module and I only care about some of the bits in the output, is there a short-hand syntax to throw away the bits? Something like

my_module module_instance
( 
 .some_output({garbage1,important1[7:0]})
);

In this case, the signal some_output in my_module is 9 bits wide, but I only want to stick the lower 8 bits into important1. I could make a signal with all 9 bits, and then just select the 8 from it, and I know the compiler will optimize it, but I'm looking for an idiom or an abbreviation.

Solution

  • If you parameterize the width of the output port in your module, then pass the parameter to the instance, there is no need to create a signal to throw away unused bits:

    my_module module_instance #(.WIDTH(8))
( 
 .some_output(important1[7:0])
);