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verilogdigital-design

How to detect the posedge of two clocks (asynchronous to each other) at the same time in verilog?

I am working on a design which should detect the first match of two rising edges of two asynchronous clocks of different frequencies.

code something like this may work for simulation.

fork 
@posedge clkA 
begin 
    a=$time 
end 
@posedge clkB 
begin 
    b=$time 
end 
join 

if (a=b) then some code.

this code may work for simulation but if I want some synthesizable hardware logic what else can I use?

Solution

  • Too pull this off, first make dual-edge,dual-clock flip-flop. Start off with a dual clock D flip-flop Patent US6320442 B1. Now substitute the sub flip-flops with dual edge D flip-flops Patent US5793236 A or Patent US5327019 A. Each patent has diagrams of the circuit design.

    With the custom flop, create a small pipeline sampling the history of the clocks. Look for a zero to one transition.

    Example:

    wire [1:0] historyA, historyB;
// dualedge_dualclock_dff     ( output Q, input D, clkA, clkB, rst_n)
dualedge_dualclock_dff dedc_histA1( .Q(historyA[1]), .D(historyA[0]), .* );
dualedge_dualclock_dff dedc_histA0( .Q(historyA[0]), .D(clkA), .* );
dualedge_dualclock_dff dedc_histB1( .Q(historyB[1]), .D(historyB[0]), .* );
dualedge_dualclock_dff dedc_histB0( .Q(historyB[0]), .D(clkB), .* );

wire dual_posedge_match = ({historyA,historyB} == 4'b0101);

    Dual-edge flops and dual-clock flops are not common design practices. Excessive timing analysis will be needed and tools might complain about the cell. Plus, steps need to be taken for patent uses compliance with the law.