I'm trying to make a UART, but the data is transferred to the z position if data is transferred from another module

Question

I'm trying to make a UART transmitter. It works if the data is initialized directly in the module; everything is output fine. But, if you transfer data from another module, then all output data is transferred to the z (high-impedance) position.

The first module from which I take the data, in an attempt to fix it, I simplified it as much as possible:

module Ever_date (
    input wire clk,          
    output wire out_date
);

    reg [7:0] date;

    always @(posedge clk) begin
    date <= 8'b0111_1101;
    end
endmodule

The second module for data transmission:

module UART_Transmitter (
input wire clk, // Clock signal
input wire [7:0] data, // Data to transfer
output reg tx // UART output signal
);
reg wirst = 1'b0;
reg data_ready = 1'b1;
reg reset = 1'b0;

reg [3:0] bit_counter = 4'd0; // Bit counter
reg [10:0] shift_reg = 11'b0; // Shift register for data

always @(posedge clk) begin
    if (reset) begin
        bit_counter <= 4'd0; // Reset the bit counter
        shift_reg <= 11'b0; // Reset the shift register
        tx <= 1'b1; // Setting the logical unit on the transmission line
    end else if (data_ready) begin
        case (bit_counter)
            4'd0: begin // Start bit
            shift_reg <= {1'b1, data}; // Generating the start bit and data
            tx <= 1'b0; // Setting a logical zero on the transmission line
            bit_counter <= bit_counter + 1; // Bit counter increment
            end
            4'd16: begin // The stop bit //16 stands because only the positive clock frequency is considered
                bit_counter <= 4'd0; // Resetting the bit counter for the next byte
            end
            default: begin // Data
                shift_reg <= {shift_reg[9:0], 1'b0}; // Data shift for transmission
                tx <= shift_reg[10]; // Sending data bits
                bit_counter <= bit_counter + 1; // Bit counter increment
            end
        endcase
    end else begin
        tx <= 1'b1; // Setting the logical unit on the transmission line if the data is not ready
    end
end

endmodule

main module:

module main
(
    input wire clkin,  
    output wire DI
);

    Ever_date Ever_date(
        .clk(clk),
        .out_date(in_tx)
    );

   UART_Transmitter uart_transmitter (  //out
         .clk(clk),
         .data(in_tx),      //in
         .tx(out_tx)        //out
    );

  assign DE = out_tx;

endmodule

I do not have a testbench. The simulation built into the ISE Design Suite was used to create this waveform:

Simplified the module from which data is transmitted to a minimum.

Answer 1

Your tool should give you warnings when you compile your code.

For example, when I compile your code on EDA playground, I get these warnings:

            4'd16: begin // The stop bit //16 stands because only the positive clock frequency is considered
                |
xmvlog: *W,INTOVF (testbench.sv,37|16): bit overflow during conversion from text [2.5(IEEE)] (4 bits).
    Top level design units:
        main
xmelab: *W,DSEMEL: This SystemVerilog design will be simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
         .data(in_tx),      //in
                   |
xmelab: *W,CUVMPW (./testbench.sv,66|19): port sizes differ in port connection(1/8) for the instance(main) .
        .out_date(in_tx)
                      |
xmelab: *W,CSINFI (./testbench.sv,61|22): implicit wire has no fanin (main.in_tx).
        .clk(clk),
               |
xmelab: *W,CSINFI (./testbench.sv,60|15): implicit wire has no fanin (main.clk).

You need to fix all these warnings in your code because they directly identify bugs in your code.

You should read the documentation for your tool to see if it has the ability to generate warnings, and if so, how you can view the warnings. If the tool does not have the capability, you need switch to a Verilog simulator such as one of the ones available on the playground.

I also recommend creating your own simple testbench: TB 101