Is a timescale or any other directive mandatory in Verilog (2001) or is its use a matter of convention or style? For example, I typically use default_nettype none to enforce explicit net declarations throughout my implementation. However, Verilog does not require me to do so.
When it comes to timescale, I obviously place it at the top of my HDL testbench. But why use it in every single module of an IP? In case of inconsistent definitions, could this lead to more problems rather than preventing them?
Generally speaking, Verilog compiler directives are not mandatory.
For timescale, refer to IEEE Std 1800-2017, section 22.7 `timescale:
If there is no timescale specified or it has been reset by a `resetall directive, the default time unit and precision are tool-specific.
The directives are global in scope, which means that when the compiler encounters one, it remains in effect for all the following code which is compiled (until another is encountered). So, there is no need to add timescale directives to all your code.
However, in practice, I have seen compilers generate errors if the 1st module (or modules) compiled does not have a timescale directive but subsequent modules do. These simulators also offer a command-line option to set the default timescale to avoid this error.