Error compiling code due to direction declaration

Question

I am running code from the internet using iverilog as follows:

example.v

 module example
      (A,B,C,D,E,F,Y);
wire t1, t2, t3, Y;

nand #1 G1 (t1,A,B);
and  #2 G2 (t2,C,~B,D);
nor  #1 G3 (t3,E,F);
nand #1 G4 (Y,t1,t2,t3);
endmodule

and example-test.v

 module testbench;
 reg A,B,C,D,E,F; wire Y;
 example DUT(A,B,C,D,E,F,Y);

 initial
 begin
  $monitor ($time," A=%b, B=%b, C=%b, D=%b, E=%b, F=%b, Y=%b", A,B,C,D,E,F,Y);
  #5 A=1; B=0; C=0; D=1; E=0; F=0;
  #5 A=0; B=0; C=1; D=1; E=0; F=0;
  #5 A=1; C=0; D=1; 
  #5 F=1;
  #5 $finish;
  end
 endmodule

I compile it using the following command

 iverilog -o mysim example.v example-test.v

and get the following errors:

 example.v:1: error: Port A (1) of module example has no direction declaration.
 example.v:1: error: Port B (2) of module example has no direction declaration.
 example.v:1: error: Port C (3) of module example has no direction declaration.
 example.v:1: error: Port D (4) of module example has no direction declaration.
 example.v:1: error: Port E (5) of module example has no direction declaration.
 example.v:1: error: Port F (6) of module example has no direction declaration.
 example.v:1: error: Port Y (7) of module example has no direction declaration.
 example.v:2: error: signal A in module testbench.DUT is not a port.
 example.v:2:      : Are you missing an input/output/inout declaration?
 example.v:2: error: signal B in module testbench.DUT is not a port.
 example.v:2:      : Are you missing an input/output/inout declaration?

Is the entire Verilog syntax in example.v code incorrect/obsolete? Why I am getting compilation errors?

The example is taken from youtube nptel verilog tutorial

Answer 1

The message is telling you that you need to declare all the module ports using a direction keyword, such as input and output, in module example. This fixes the errors:

module example
      (A,B,C,D,E,F,Y);
      input A,B,C,D,E,F;
      output Y;
wire t1, t2, t3;

nand #1 G1 (t1,A,B);
and  #2 G2 (t2,C,~B,D);
nor  #1 G3 (t3,E,F);
nand #1 G4 (Y,t1,t2,t3);
endmodule

About 28 minutes into the video, the example code is correct because it uses input and output. The code you copied shows up later in the video, and it is incorrect.

Note that there is no need to also declare Y as a wire.

---

A more concise way which avoids duplicating the port names is as follows:

module example (
    input A,B,C,D,E,F,
    output Y
);
wire t1, t2, t3;

nand #1 G1 (t1,A,B);
and  #2 G2 (t2,C,~B,D);
nor  #1 G3 (t3,E,F);
nand #1 G4 (Y,t1,t2,t3);
endmodule