Verilog - bitstream works on hardware but simulation doesn't compile

Question

I am using Verilog to set up FPGA so that it blinks an LED once per second. And this is one way to do it:

`default_nettype none

module pps(i_clk, o_led);

    parameter CLOCK_RATE_HZ = 12_000_000;

    input wire i_clk;
    output wire o_led;

    reg [23:0] counter;
    initial counter = 0;

    always @(posedge i_clk)
        if (counter < CLOCK_RATE_HZ/2 - 1)
            begin
                counter <= counter + 1'b1;
            end
        else
            begin
                counter <= 0;
                o_led <= !o_led;
            end
    
endmodule

Now I wrote this makefile:

file_v = pps
file_pcf = icebreaker
file_cpp = driver
module_top = pps

all:
    yosys -p "synth_ice40 -top $(module_top) -blif $(file_v).blif" $(file_v).v
    arachne-pnr -d 5k -P sg48 -o $(file_v).asc -p $(file_pcf).pcf $(file_v).blif
    icepack $(file_v).asc $(file_v).bin

flash:
    iceprog $(file_v).bin

simulate:
    verilator --trace -Wall -cc $(file_v).v
    make -C obj_dir -f V$(file_v).mk
    
    g++ \
    -I /usr/share/verilator/include/ \
    -I obj_dir/ \
    /usr/share/verilator/include/verilated.cpp \
    /usr/share/verilator/include/verilated_vcd_c.cpp \
    $(file_cpp).cpp \
    obj_dir/V$(file_v)__ALL.a \
    -o $(file_v).elf
    
    ./$(file_v).elf
    
    gtkwave $(file_v).vcd

#################################################################################################

.PHONY: clean
clean:
    @rm *.bin
    @rm *.blif
    @rm *.asc
    @rm -r obj_dir
    @rm *.elf
    @rm *.vcd

First two makefile targets (all & flash) work flawlesly, and when bitstream file is uploaded to the board, LED flashes at 1Hz. Nice.

But, when I try to simulate this module, I run makefile target simulate, and I get an error:

┌───┐
│ $ │ ziga > ziga--workstation > 003--pps
└─┬─┘ /dev/pts/13
  └─> make simulate
verilator --trace -Wall -cc pps.v
%Error-PROCASSWIRE: pps.v:72: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): o_led
%Error: Exiting due to 1 error(s)
%Error: See the manual and http://www.veripool.org/verilator for more assistance.
%Error: Co`

Can somebody explain what is wrong? The design already works on hardware (!), so why wouldn't my simulation compile? How do I make this example also work for the simulation?

Answer 1

As your error message states, it is illegal to make a procedural assignment to a wire. A procedural assignment is an assignment made inside an always block, for example. You declared o_led as a wire, but then you assigned to it in an always block. You should use a reg type inside an always block. Refer to IEEE Std 1800-2017, section 10.4 Procedural assignments.

Change:

output wire o_led;

to:

output reg o_led;

wire types are used for continuous assignments, using the assign keyword, for example.