For a university class, we were told to do an 8-bit full_adder out of full_adders and a test. I believe the main code is correct, but I might have done some errors on the test. I would really appreciate if I could get some help with the x output.
here is the 8-bit adder:
module adder_8bit (A1, B1, A2, B2, A3, B3, A4, B4, A5, B5, A6, B6, A7, B7, A8, B8, C_IN,
S_OUT1, C_OUT1, S_OUT2, C_OUT2, S_OUT3, C_OUT3, S_OUT4, C_OUT4, S_OUT5, C_OUT5, S_OUT6, C_OUT6, S_OUT7, C_OUT7, S_OUT8, C_OUT8,
S0, D0, C0, S1, D1, C1, S2, D2, C2, S3, D3, C3, S4, D4, C4, S5, D5, C5, S6, D6, C6, S7, D7, C7 );
input A1, B1, A2, B2, A3, B3, A4, B4, A5, B5, A6, B6, A7, B7, A8, B8, C_IN;
inout C_OUT1, S_OUT2, C_OUT2, S_OUT3, C_OUT3, S_OUT4, C_OUT4,
S_OUT5, C_OUT5, S_OUT6, C_OUT6, S_OUT7, C_OUT7, S_OUT8,S0, D0, C0, S1, D1, C1,
S2, D2, C2, S3, D3, C3, S4, D4, C4, S5, D5, C5, S6, D6, C6, S7, D7, C7;
output S_OUT1, C_OUT8;
assign S0 = A1 ^ B1;
assign C0 = A1 & B1;
assign S_OUT1 = S0 ^ C_IN;
assign D0 = S0 & C_IN;
assign C_OUT1 = D0 | C0;
assign S1 = A2 ^ B2;
assign C1 = A2 & B2;
assign S_OUT2 = S1 ^ C_OUT1;
assign D1 = S1 & C_OUT1;
assign C_OUT2 = D1 | C1;
assign S2 = A3 ^ B3;
assign C2 = A3 & B3;
assign S_OUT3 = S2 ^ C_OUT2;
assign D2 = S2 & C_OUT2;
assign C_OUT3 = D2 | C2;
assign S3 = A4 ^ B4;
assign C3 = A4 & B4;
assign S_OUT4 = S3 ^ C_OUT3;
assign D3 = S3 & C_OUT3;
assign C_OUT4 = D3 | C3;
assign S4 = A5 ^ B5;
assign C4 = A5 & B5;
assign S_OUT5 = S4 ^ C_OUT4;
assign D4 = S4 & C_OUT4;
assign C_OUT5 = D4 | C4;
assign S5 = A6 ^ B6;
assign C5 = A6 & B6;
assign S_OUT6 = S5 ^ C_OUT5;
assign D5 = S5 & C_OUT5;
assign C_OUT6 = D5 | C5;
assign S6 = A7 ^ B7;
assign C6 = A7 & B7;
assign S_OUT7 = S6 ^ C_OUT6;
assign D6 = S6 & C_OUT6;
assign C_OUT7 = D6 | C6;
assign S7 = A8 ^ B8;
assign C7 = A8 & B8;
assign S_OUT8 = S7 ^ C_OUT7;
assign D7 = S7 & C_OUT7;
assign C_OUT8 = D7 | C_OUT7;
endmodule
and here is the test
`include "adder_8bit.v"
`timescale 1ps/1ps
module adder_8bit_test;
reg A1, B1, A2, B2, A3, B3, A4, B4, A5, B5, A6, B6, A7, B7, A8, B8, C_IN;
wire C_OUT1, S_OUT2, C_OUT2, S_OUT3, C_OUT3, S_OUT4, C_OUT4,
S_OUT5, C_OUT5, S_OUT6, C_OUT6, S_OUT7, C_OUT7, S_OUT8, S0, D0, C0, S1, D1, C1,
S2, D2, C2, S3, D3, C3, S4, D4, C4, S5, D5, C5, S6, D6, C6, S7, D7, C7,
S_OUT1, C_OUT8;
adder_8bit UUT (.A1, .B1, .A2, .B2, .A3, .B3, .A4, .B4, .A5, .B5, .A6, .B6, .A7, .B7, .A8, .B8,
.S_OUT1, .C_OUT1, .S_OUT2, .C_OUT2, .S_OUT3, .C_OUT3, .S_OUT4, .C_OUT4, .S_OUT5, .C_OUT5, .S_OUT6, .C_OUT6, .S_OUT7, .C_OUT7, .S_OUT8, .C_OUT8,
.S0, .D0, .C0, .S1, .D1, .C1, .S2, .D2, .C2, .S3, .D3, .C3, .S4, .D4, .C4, .S5, .D5, .C5, .S6, .D6, .C6, .S7, .D7, .C7 );
initial begin
$display("Start of Test.");
$dumpfile("adder_8bit.vcd");
$dumpvars(0, adder_8bit_test);
{A1, B1, C_IN} = 3'b000; #100; $display("%b + %b + %b = %b%b", A1, B1, C_IN, S_OUT1, C_OUT1);
{A1, B1, C_IN} = 3'b001; #100; $display("%b + %b + %b = %b%b", A1, B1, C_IN, S_OUT2, C_OUT2);
{A1, B1, C_IN} = 3'b010; #100; $display("%b + %b + %b = %b%b", A1, B1, C_IN, S_OUT3, C_OUT3);
{A1, B1, C_IN} = 3'b011; #100; $display("%b + %b + %b = %b%b", A1, B1, C_IN, S_OUT4, C_OUT4);
{A1, B1, C_IN} = 3'b100; #100; $display("%b + %b + %b = %b%b", A1, B1, C_IN, S_OUT5, C_OUT5);
{A1, B1, C_IN} = 3'b101; #100; $display("%b + %b + %b = %b%b", A1, B1, C_IN, S_OUT6, C_OUT6);
{A1, B1, C_IN} = 3'b110; #100; $display("%b + %b + %b = %b%b", A1, B1, C_IN, S_OUT7, C_OUT7);
{A1, B1, C_IN} = 3'b111; #100; $display("%b + %b + %b = %b%b", A1, B1, C_IN, S_OUT8, C_OUT8);
$display("End of Test.");
end
endmodule
I get a compile warning; if you do not, you should sign up for a free account on edaplayground and try to compile your code there on multiple simulators.
You did not drive your C_IN input. Change:
adder_8bit UUT (.A1, .B1, .A2, .B2, .A3, .B3, .A4, .B4, .A5, .B5, .A6, .B6, .A7, .B7, .A8, .B8,
to:
adder_8bit UUT (.A1, .B1, .A2, .B2, .A3, .B3, .A4, .B4, .A5, .B5, .A6, .B6, .A7, .B7, .A8, .B8, .C_IN,
You also need to set all your inputs to known values. You only set A1, B1 and C_IN.
A2, A3, etc., are all unknown (x). Perhaps you meant to use something like this:
{A1, B1, C_IN} = 3'b000; #100; $display("%b + %b + %b = %b%b", A1, B1, C_IN, S_OUT1, C_OUT1);
{A2, B2, C_IN} = 3'b001; #100; $display("%b + %b + %b = %b%b", A2, B2, C_IN, S_OUT2, C_OUT2);
Other considerations:
inout there.reg [7:0] A;