Search code examples
verilogyosys

How to unpack LUTs into logic cells in verilog

I have a structural verilog containing LUTS all over him.

I want this verilog to be unpacked so that I'll have the same functional but instead LUTS - I'll have logic cell (Like Or/And/Xor etc...).

How can I do it ?

Does Yosys has something built in ? Is there something else out there over the internet who already implement that kind of thing ? Because I searched for this and I could not find.

Solution

  • You could do something like the following

    read_verilog struct.v lut.v
hierarchy -top top
flatten
synth -noabc

    in Yosys, where lut.v contains a Verilog model of the LUT primitive. This would convert LUTs to non-optimised logic. You could also use abc (remove -noabc, or add abc at the end of the script) to optimise the logic.