I am trying to get default parameter values for verilog modules using Yosys command shell. Is there any way to do it? In addition, is parsing a `write_ilang' command output file a good idea or its format can change dramatically in the near future?
Attempts were made to find default values in ilang, json, table dumps and even using chparam -list
command, but they did not bring any result.
Consider this example (file param_test.v):
module stub();
parameter PUBLIC_PARAM = 1;
parameter HIDDEN_PARAM = 2;
endmodule
module testbench();
stub no_param_stub ();
stub #(.PUBLIC_PARAM(1)) one_param_stub ();
endmodule
I follow these steps:
read -sv param_test.v
hierarchy -top testbench
Output from write_ilang
command:
# Generated by Yosys 0.8+634 (git sha1 ac2fc3a, clang 3.8.0-2ubuntu4 -fPIC -Os)
autoidx 1
attribute \blackbox 1
attribute \src "param_test.v:1"
module $paramod\stub\PUBLIC_PARAM=1
parameter \HIDDEN_PARAM
parameter \PUBLIC_PARAM
end
attribute \blackbox 1
attribute \src "param_test.v:1"
module \stub
parameter \HIDDEN_PARAM
parameter \PUBLIC_PARAM
end
attribute \top 1
attribute \src "param_test.v:6"
module \testbench
attribute \module_not_derived 1
attribute \src "param_test.v:8"
cell \stub \no_param_stub
end
attribute \module_not_derived 1
attribute \src "param_test.v:10"
cell $paramod\stub\PUBLIC_PARAM=1 \one_param_stub
end
end
Output from write_json
command does not even contain information about the HIDDEN_PARAM
parameter:
{
"creator": "Yosys 0.8+634 (git sha1 ac2fc3a, clang 3.8.0-2ubuntu4 -fPIC -Os)",
"modules": {
"$paramod\\stub\\PUBLIC_PARAM=1": {
"attributes": {
"blackbox": 1,
"src": "param_test.v:1"
},
"ports": {
},
"cells": {
},
"netnames": {
}
},
"stub": {
"attributes": {
"blackbox": 1,
"src": "param_test.v:1"
},
"ports": {
},
"cells": {
},
"netnames": {
}
},
"testbench": {
"attributes": {
"top": 1,
"src": "param_test.v:6"
},
"ports": {
},
"cells": {
"no_param_stub": {
"hide_name": 0,
"type": "stub",
"parameters": {
},
"attributes": {
"module_not_derived": 1,
"src": "param_test.v:8"
},
"port_directions": {
},
"connections": {
}
},
"one_param_stub": {
"hide_name": 0,
"type": "$paramod\\stub\\PUBLIC_PARAM=1",
"parameters": {
},
"attributes": {
"module_not_derived": 1,
"src": "param_test.v:10"
},
"port_directions": {
},
"connections": {
}
}
},
"netnames": {
}
}
}
}
Yosys recently gained the functionality to preserve parameters through elaboration (whereas they are usually thrown away). Add -pwires
to read_verilog
and parameters will be converted into wires driven by the parameter's default value with the parameter
attribute set to 1.
In terms of stability, there are several other tools (such as nMigen) that create or read RTLIL ilang, so it is unlikely to have significant breaking changes now.