Increment integer under case state in verilog with yosys

Question

I don't know if it's in Verilog-2005 standard but I managed to compile following code with «synplify pro» and «icarus verilog».

  integer fsm_step_number;

  always @(posedge clk or posedge rst)
    if(rst) begin
      pc <= 8'h00;
      wb_addr_o <= 8'h00;
      wb_wdat_o <= 8'h00;
      wb_stb_o  <= 1'b0;
      wb_cyc_o  <= 1'b0;
      wb_we_o   <= 1'b0;
      temt <= 1;
    end
    else begin
        fsm_step_number=1;
        case(pc)
                       fsm_step_number++: begin 
                          wb_addr_o <= UART_LSR;
                          wb_stb_o  <= 1'b1;
                          wb_cyc_o  <= 1'b1;
                          wb_we_o <= 1'b0;
                       end

                       fsm_step_number++: begin 
                          temt <= wb_rdat_i[6];
                          wb_stb_o  <= 1'b0;
                          wb_cyc_o  <= 1'b0;
                          wb_we_o <= 1'b0;
                       end
                 [...]
         endcase
 end

The incrementation of fsm_step_number integer doesn't works with lattice synthesis program (LSE) neither Yosys. I have a syntax error with yosys :

yosys> read_verilog uart_ctrl_pre.v 
1. Executing Verilog-2005 frontend.
Parsing Verilog input from `uart_ctrl_pre.v' to AST representation.
ERROR: Parser error in line uart_ctrl_pre.v:74: syntax error, unexpected TOK_INCREMENT

Do you know if it's possible to do a think like that with Yosys (increment integer into case state) ?

Answer 1

The ++ operator is in SystemVerilog, not Verilog. And I think that synthesis tools require that the either the case(expression) or list of item: expressions be a constant, but do not allow both to be non-constant expressions.