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verilogsynthesisyosys

is nested @ supported?

I am trying to create an implicit FSM using the following syntasix:

always @(posedge clock) begin
   @(posedge clock)begin
       statement
   end
   @(posedge clock)begin
       statement
   end

It works fine in simulation but when I try to synthesize, an error displays: "syntax unexpected @"

is this sintax not supported by yosys?

THX

Solution

  • A high-level synthesis tool can support this and build a state machine from multiple clock edges in a single always block. But I don't think yosys can handle it.