I am using YOSYS to convert Verilog to BLIF. Input is a circuit (L_0_0) that only contains not, and, or primitives and some behavioral latching code.
The commands I use are:
> read_verilog <file>
> proc; opt; memory; opt; techmap; opt;
> write_blif <file>
The output file contains $_DFF_PN0_ as a .subckt with no .model, so when I input this file to MVSIS, it ignores all the subckts.
How can I map this sub circuit to somewhat known by other tools?
.model L_0_0
.inputs clk rst ce ins
.outputs outs
.names $false
.names $true
1
.names $undef
.names outs r_out_1_0 ce $0\outs[0:0]
1-0 1
-11 1
.names r_out_2_0 w_out_2_0 ce $0\r_out_2_0[0:0]
1-0 1
-11 1
.names r_out_1_0 w_out_1_0 ce $0\r_out_1_0[0:0]
1-0 1
-11 1
.names r_out_0_0 w_out_0_0 ce $0\r_out_0_0[0:0]
1-0 1
-11 1
.subckt $_DFF_PN0_ C=clk D=$0\outs[0:0] Q=outs R=rst
.subckt $_DFF_PN0_ C=clk D=$0\r_out_0_0[0:0] Q=r_out_0_0 R=rst
.subckt $_DFF_PN0_ C=clk D=$0\r_out_1_0[0:0] Q=r_out_1_0 R=rst
.subckt $_DFF_PN0_ C=clk D=$0\r_out_2_0[0:0] Q=r_out_2_0 R=rst
.names r_out_0_0 r_out_1_0 w_out_0_0
1- 1
-1 1
.names r_out_2_0 r_out_2_0 w_out_1_0
1- 1
-1 1
.names r_out_0_0 ins w_out_2_0
1- 1
-1 1
.names r_out_0_0 w_in_0_0
1 1
.names r_out_1_0 w_in_0_1
1 1
.names r_out_2_0 w_in_1_0
1 1
.names r_out_2_0 w_in_1_1
1 1
.names r_out_0_0 w_in_2_0
1 1
.names ins w_in_2_1
1 1
.end
New output with sync reset is below. Verilog output ports are all connected and seems that they are connected in BLIF too.
# Generated by Yosys 0.7 (git sha1 61f6811, i686-w64-mingw32.static-gcc 4.9.3 -Os)
.model L_0_0
.inputs clk rst ins
.outputs outs
.names $false
.names $true
1
.names $undef
.names r_out_0_0 $false rst $0\outs[0:0]
1-0 1
-11 1
.names w_out_1_0 $false rst $0\r_out_1_0[0:0]
1-0 1
-11 1
.names w_out_0_0 $false rst $0\r_out_0_0[0:0]
1-0 1
-11 1
.latch $0\outs[0:0] outs re clk 2
.latch $0\r_out_0_0[0:0] r_out_0_0 re clk 2
.latch $0\r_out_1_0[0:0] r_out_1_0 re clk 2
.names r_out_0_0 r_out_1_0 w_out_0_0
11 1
.names ins r_out_1_0 w_out_1_0
1- 1
-1 1
.names r_out_0_0 w_in_0_0
1 1
.names r_out_1_0 w_in_0_1
1 1
.names ins w_in_1_0
1 1
.names r_out_1_0 w_in_1_1
1 1
.end
The BLIF file format does not support storage elements with asynchronous resets. Unfortunately you do not post the Verilog code you used as input, but from what you have posted it is obvious that your Verilog does contains such storage elements. ($_DFF_PN0_ is a Yosys internal cell type used to represent a positive-edge flip-flop with negative polarity asynchronous reset-to-zero. Yosys just outputs that cell as it is since there is no equivalent construct for that in BLIF.)
If you would like to use BLIF output then you'll have to avoid using asynchronous resets in your design. There is nothing Yosys can do here because this is a limitation of the BLIF file format.
If you do not want to change the HDL code, but are fine with converting the asynchronous resets to synchronous resets, then you can simply run techmap -map +/adff2dff.v after running proc.