Verilog - Nested generate for loop with multiple genvars, not possible?

Question

I'm trying to add a second level of nesting to my generate loop in the following code, but iverilog is throwing an error that the register j is unknown:

../crc.v:119: register ``j'' unknown in crc_tb.U_crc.loop[31].

So is it possible to use multiple genvars in verilog? It looks like j is being interpreted as a register.

Code snippet:

genvar i;
genvar j;

reg [DATA_WIDTH-1:0] temp;

generate
for(i = 0; i < CRC_WIDTH; i= i + 1)
begin : loop
    always @(posedge clock or posedge reset)
    begin
         if (reset)
         begin
             crc_out[i+:1] = SEED[i+:1];
         end
         else if (init)
         begin
            crc_out[i+:1] = SEED[i+:1];
         end
         else if (data_enable)
         begin
            if (DEBUG)
                 $display("\n\nCRC OUT[%0d]\n***************************************************************************", i); 
            if (REVERSE)
            begin
                for (j = DATA_WIDTH-1; j >= 0; j = j - 1)
                begin : reverse_loop
                    temp[DATA_WIDTH-1-j]  = data[i][j];
                end
                crc_out[i+:1] <= prev(DATA_WIDTH-1,i,temp,crc_out);                
            end
            else
            begin
                crc_out[i+:1] <= prev(DATA_WIDTH-1,i,data,crc_out);
            end
         end
     end
end
endgenerate

Answer 1

You can nest multiple generate loops, but your inner generate loop is inside a procedural block of code - that is illegal. Perhapsj should just be a local variable instead of a genvar.