I'm trying to make a testbench to simulate a working top level module (and child module) however I can't get iverilog to handle the output of top correctly (LEDS,RS232Rx and RS232Tx are physical pins)
here's my attempt at a testbench
module test();
initial begin
$dumpfile("test.vcd");
$dumpvars(0,test);
# 1024 $stop;
end
reg clk = 0; always #1 clk = !clk;
//reg rx,tx;
reg [7:0] opl;
top top1 ( .clk(clk), .RS232Rx(rx), .RS232Tx(tx), .LEDS(opl) );
endmodule
I'm seeing error like this
iverilog -o test-design testbench.v top.v
top.v:47: error: LEDS is not a valid l-value in test.top1.
top.v:8: : LEDS is declared here as wire.
testbench.v:10: error: reg opl; cannot be driven by primitives or continuous assignment.
testbench.v:10: error: Output port expression must support continuous assignment.
testbench.v:10: : Port 4 (LEDS) of top is connected to opl
3 error(s) during elaboration.
I've tried alsorts of things but with not much in the way of an illuminating or different error message, the best LEDS as a testbench output, showing only an error in top.v which is working... I see very similar errors with rx,tx but commented them out to make a shorter output...
just to reiterate top.v does, not only synthesize but behaves exactly as expected on actual hardware
Turns out that despite my top level design was able to output to a wire, iverilog wasn't happy to do this,
adding
reg [7:0] leds;
assign LEDS=leds;
allows my top level design to work on hardware (as before), but also iverilog (icarus) now seems able to deal with it...