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verilog

Parallel execution of module under always block

I have written a module in Verilog implementing a D flip-flop, like the following:

module d_flip_flop(q,d,clk,reset);

Now, I want to implement a 4-bit shift register using this module. So I have to execute four d flip flops in parallel inside always @(negedge clk) block. I don't know how to parallel execute four user defined modules inside always (or how to instantiate). I don't want a direct behavioral implementation of a 4-bit shift register.

Solution

  • One way is to create 4 instances, connecting the q output of one to the d input of the next:

    wire [3:0] q;
d_flip_flop i0 (q[0], din , clk,reset);
d_flip_flop i1 (q[1], q[0], clk,reset);
d_flip_flop i2 (q[2], q[1], clk,reset);
d_flip_flop i3 (q[3], q[2], clk,reset);

    There is no need to use an always block.