In Verilog, how to "hold" the value of the rest of a register while modifying a single bit?

Question

In Verilog HDL, how can I enforce that the rest of a register file to be untouched while I'm modifying a single bit? Like in the following example,

reg [31:0] result;
reg [31:0] next_result;
reg [4:0] count;
wire done;

//some code here...

result <= 32'b0;

always @* begin
if(done==1'b1) begin
  next_result[count] <= 1'b1;
end
end

always @(posedge clock) begin
result <= next_result;
//the rest of the sequential part, in which count increments...
end

it turns out that result contains lots of x(unknown) values after several cycles, which means the register file is not held constant while I am modifying result[count]. Weird though, this problem is only present while I'm synthesizing, and everything goes just fine for simulation purposes. I wonder if there is some way to tell the synthesizer that I would like to "enforce" that not changing the rest of the register file.

Answer 1

You never assign all the bits inside the combinatorial loop. you have a floating assignment result <= 32'b0; I am surprised that this compiles. There is also an implied latch by not having next_result assigned in an else statement, ie when done=0 next_result would hold its value.

Try:

always @* begin
  if(done==1'b1) begin
    next_result        = result;
    next_result[count] = 1'b1;
  end
  else begin
    next_result        = result;
  end
end

OR

always @* begin
  next_result = result;
  if(done==1'b1) begin
    next_result[count] = 1'b1;
  end
end

You have also used non-blocking <= assignments in the combinatorial loop.