I have a relatively simple circuit that I'm trying to compile. It requires 491 I/O pins, so I'm selecting a non-default device that has more than 456 (Cyclone IV GX with 508 user I/Os). The problem is that when compiling I receive this error:
Error: Can't place 489 pins with 1.2 V I/O standard because Fitter has only 380 such free pins available for general purpose I/O placement
I'm not sure what this 380 free pins mean, I'm sure that the I/O pins should be enough, I can see it in the report:
Total Pins 491 / 508 ( 97 % )
I think that is probably because it's talking about some other type of pin I'm not aware of (I'm just starting with electronics and VHDL).
Not all pins on a given FPGA can support every I/O standard. That error message indicates that there are only 380 pins that support 1.2V I/O pins. You will need to assign some of your pins to a standard that is compatible with the other pins. The device documentation or Quartus should have documentation on which pins support what I/O standards.