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vhdlsimulationverilogsynthesis

mixed VHDL & Verilog designs: which free simulation and/or synthesis tools?

I'm developping a mixed-hdl design using VHDL and Verilog IP's.

Which tool can I use to simulate and synthetize it for free if my target FPGA vendor is not chosen yet?

Solution

  • Xilinx ISIM certainly can do mixed language simulations. Last time I used it much, there were limitations : I could only add Verilog memory models to the top level of my VHDL design, not in a sub-level (representing a SODIMM module) and there were some stupid port connection bugs, possibly now fixed.

    Avoid using Xilinx IP and it'll simulate vendor neutral code, though technically that may violate the license agreement.

    Post-synthesis netlists may be in either language, but if your memory models are only available in Verilog and your testbenches are VHDL, that doesn't help much...