Recently, I did some rtl practice like divider and sequence detector. I used the same sdc file to synthesis and it comes from an open source project.(Project link) The following codes come from the sdc file using in the open source project and also used in my practice.
# operating conditions and boundary conditions #
create_clock -name clk -period 30.0 [get_ports clk]
set_dont_touch_network [all_clocks]
set_fix_hold [all_clocks]
set_clock_uncertainty 0.1 [all_clocks]
set_clock_latency 0.5 [all_clocks]
set_ideal_network [get_ports clk]
#Don't touch the basic env setting as below
set_input_delay 5.0 -clock clk [remove_from_collection [all_inputs] [get_ports clk]]
set_output_delay 0.5 -clock clk [all_outputs]
set_load 1 [all_outputs]
set_drive 1 [all_inputs]
set_operating_conditions -max_library slow -max slow
set_wire_load_model -name tsmc13_wl10 -library slow
set_max_fanout 20 [all_inputs]
Since I never take part in a complete IC design or ASIC design, so I really don't know where these constraint values come from. To be specific, the property of clock like uncertainty and latency, how to decide its value? Did someone tell you its value or you should make some effort to get the value by yourself? Same question about the load, drive and fanout.
Several of these constraint values listed depend on the physical hardware (the board and its components) which hosts the physical programmable logic (ASIC, FPGA, etc) device. RTL coders work with hardware engineers or other engineering rolls who are more familiar with what is physically connected to the programmable logic device in order to determine the correct constraint value.
set_clock_uncertainty depends on the jitter associated with the oscillator (a board component) which creates the clock. The board hardware engineer would have info on the oscillator. The original info on he oscillator would come from its data sheet.
set_clock_latency depends on the board and traces which establish the delay between the oscillator output pin, and the programmable logic input pin. The board hardware engineer would have info on the delay. The delay information would come from an analysis performed on the board layout.
set_load and set_drive defines the programmable logic output pin characteristics. These depend on what is connected to the programmable logic device output pin. For example a connected LED would require stronger drive strength (current), and have a larger load (capacitance) than a single pin of another integrated circuit chip (example a DRAM chip) located near the programmable logic on the board. The board hardware engineer would have info on the output pin loading & drive. This information would originate in the data sheet for whatever component is connected to the output pin of interest.
set_max_fanout This constraint depends on the physical programmable logic device itself, and would have a default or range for a particular programmable logic device technology. Its value depends on transistor level and layout design choices for the device. Consult the devices documentation or a subject matter expert on the particular device's physical design to determine its value. Increasing or decreasing the value would lead to trade-offs in performance, power, and area for the programmable logic device. It seems like this could also be applied to output pin fanout (why not; perhaps other constraints cover output pins?), I have only seen it used internally to the programmable logic device.