How do I get rid of sensitivity list warning when synthesizing Verilog code?

Question

I am getting the warning that:

One or more signals are missing in the sensitivity list of always block.

always@(Address)begin
  ReadData = instructMem[Address];
end

How do I get rid of this warning?

Answer 1

Verilog does not require signal names in the sensitivity list. Use the @* syntax to signify that the always block should be triggered whenever any of its input signals change:

always @* begin 
    ReadData = instructMem[Address]; 
end