I have completed on a project making physical logic gates and am now looking for a way to turn an arbitrary program into some series of logic gates so I can use them.
I need a program that can take some arbitrary function (say f= x^2 -1) directly into some series of logic gates. Does this already exist?
I have found Verilog and several other open source options but they do not appear to output circuit diagrams. There is also Quartus II and other programs which will convert VHDL code into a schematic.
Preferably I would like something that compiles Python/C++ to a logic gate schematic directly - but really any language is fine.
Thanks.
EDIT: I do mean physical gates - they use ball bearings!
I have all of the 1-bit-input/1-bit-output gates and all of the 2-bit-input/1-bit output-gates. From these I can also construct a MAJ gate to do error correction.
Write your arbitrary code in VHDL, turning VHDL into gates is what a synthesis tool does.
Not everything you write will be synthesisable; file handling can't be translated into gates, neither can anything that conventionally uses the heap (such as malloc, or pointers, in C, or "new" and access types in VHDL). Floating point can be synthesised (with VHDL-2008) but it's not quite as simple as signal A : Real; A <= 2.0 * X * X - 1.0; you have to use types from the synthesisable floating point library. So there may be some negotiation with the tool about the programming language subset you can use.
But I'm sensing a slightly different question here : how do I translate arbitrary code into MY logic gates, implemented in (technology not described in the question). And that's harder to answer.
Synthesis tools usually come from a vendor such as an FPGA vendor, and they translate arbitrary code into that vendor's logic gates, not yours.
The ideal solution is to create a library describing your logic technology, which plugs into a vendor-neutral synthesis tool, such as Synplicity from Synopsys. Then Synplicity can synthesise to your technology instead of an FPGA vendor's.
OK, but creating that library is likely to be a task roughly on a par with writing a backend for a custom CPU's instruction set, and integrating that backend into gcc. Except that Synplicity, unlike gcc, isn't open source, so without considerable financial and technical resources, and help and internal documentation from a major EDA tool company, it's approximately impossible. (At this point I'd be delighted to be corrected by someone who's actually done it)
EDIT (nearly 7 years later!)
GHDL (open source VHDL simulator) available from Github has grown a synthesis branch, so this route is now likely to be easier (I'll stop short of saying easy!) or may be a better choice than a proprietary toolset for the route below. It has a tie-in to the YOSYS open source synthesis suite. CAVEAT : I haven't tried it, but it may be worth a look for future viewers of this question.
(end edit)
So we need a different approach.
Back to the FPGA synth tools : I'll use Xilinx XST as an example. It'll synth to Xilinx primitives, in some Xilinx closed internal format.
However there's also an option labelled "Write post-synthesis netlist".
Using that, you can get a structural VHDL file representing the translation of your arbitrary code into Xilinx gates, flip-flops, and other elements, which are drawn from the Simprims library.
Attempt to compile that (e.g. in a simulator) without making the Simprims library visible (e.g. with the library Simprims; use Simprims; statements commented out and you'll get something valuable:
a list of compilation errors
Not so valuable, you may think : except that it's actually a list of gates, flipflops and other elements that are needed to implement your design.
If you can find (or create) a one-to-one correspondence between these, and elements in your chosen technology, then you can map this netlist to your technology.
If there are Simprims elements for which you don't have equivalents, you need to implement them - e.g. by creating 3-input AND gates from networks of the 2-input NAND gates you have.
Use the corresponding elements from your own (VHDL) library, instead of Simprims, and you should, in theory, have a usable compiled design.
(You're on your own with problems like layout, routing, timing analysis. This is not trivial, but for the sake of this question I'm assuming your "project making physical gates" has these covered...)