Is indexing into an array with a signal synthesizable in verilog?

Question

Are there any problems with synthesizing the following?:

 // Read entry
  assign entry[7:0] = my_array[read_address[10:0]][7:0];

Where read_address is a signal being used to read my_array.

I'm used to AND-OR logic for reading an array but I was wondering if the above is 1) synthesizable and 2) what kind of logic it would create?

Answer 1

Yes, you can use another variable or expression as an index into an array. The catch is you are only allowed to do this on the RHS of a continuous assignment. You would not be allowed to do the reverse

assign my_array[read_address[10:0]] = entry; // illegal

Also, there is no need to select [7:0] if that is the entire range of the element or signals. In fact that causes problems with signed signals making them unsigned operands.