Flip flop reset with ternary operator instead of if-else statement

Question

I am wondering if it is OK to replace flip flop resets with the ternary operator to minimize line count and improve readability. Does the RTL below have the same effect in simulation and synthesis?

always_ff @(posedge clk, posedge ares) begin
   if (ares) begin
      signal <= a;
   end
   else begin
      signal <= b;
   end 
end

compared with:

always_ff @(posedge clk, posedge ares) begin
   signal <= ares ? a : b;
end

How about for the case of synchronous reset?

Answer 1

You should expect both versions of your code to simulate the same way.

Synthesis results are likely to be dependent upon the tool you are using. The code example with the if/else maps to a conventional synthesis construct for a flip flop (if a is a constant, like a parameter). The code example with the ternary may not be supported by synthesis tools. Refer to your synthesis tool documentation to see what Verilog code patterns are allowed.