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verilogsystem-verilogclockuvm

clock switching in systemverilog test-bench

In order to verify my block's DVFS feature, the clock to DUT should switch based on one event. for example, if the control register updated to fast mode, my TB need increase the clock frequency, if the control register updated to slow mode, my TB need decrease the clock frequency.

How can I do this with systemverilog in TB? In my simple TB, the clock is always at a fixed frequency.

Solution

  • You can control your clock frequency with a variable period in your testbench

    bit clk;
real period = 10ps;
initial forever
   #(period/2.0) clk = !clk;

    If your testbench is updating the control register, then it can also the period. Since you tagged this with UVM what people normally do is create an interface for driving the clock and reset, and a sequence to control the frequency and apply reset. Then put the code I wrote above in an interface, and the driver can set the period through a virtual interface.