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structverilogsystem-verilogregister-transfer-level

Anonymous struct export to top


I have an input SystemVerilog RTL like this :

typedef struct packed {
  logic [1:0][3:0] a;
  struct packed {
    logic [4:0] b;
    logic c;
    logic [1:0] d;
  }  e; // anonymous packed struct field
} s0;

module ip( input s0  p );
endmodule

module top();
endmodule

Using some scripts I want :

  • To export (from ip to top) the the field p.e, i.e generate something like :
    typedef struct packed { 
         logic [4:0] b; 
         logic c; 
         logic [1:0] d; 
    } s0_e; 
    module top(s0_e p);
    
  • Then connect ip inside top with : ip.p.e <->top.p (and ip.p.a left unconnected)

Given that p.e is an anonymous struct I am wondering what would be the correct syntax to do it? do I need to create a new typedef as above ?


Solution

  • In general, you should avoid using anonymous strucures if you want to share information between modules. But since this is a packed struct, there is no type safety and it doesn't matter if you declare the types independently. They just need to have the same number of bits.

    typedef struct packed {
        logic [4:0] b;
        logic c;
        logic [1:0] d;
    }  et; 
    typedef struct packed {
      logic [1:0][3:0] a;
      et e;}
    s0;
    
    module ip( input wire s0  p );
    endmodule
    
    module top(input wire et p); 
    
      s0 signal;
      assign signal.e = p;
      
      ip inst(signal);
      
    endmodule