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system-veriloguvmsystem-verilog-assertions

how to use assertoff from test to disable assertion in side uvm object


I am looking for way to disable assert in side uvm component for certain test. Below simple code represent my env, with comment for requirement. I thought I can use $assertoff. I can modify uvm component if required additional instrumentation to achieve this.

    import uvm_pkg::*;
    `include "uvm_macros.svh"

    class tb_env extends uvm_component;

       `uvm_component_utils(tb_env)

       int exp_val = 0;
       int act_val = 0;

       function new(string name = "tb_env", uvm_component parent = null);
          super.new(name, parent);
       endfunction

       virtual task run_phase (uvm_phase phase);
         super.run_phase(phase);
         phase.raise_objection(this);
         #10us;
         ASRT: assert ( exp_val == act_val) else
           `uvm_error(get_name(), "Error");
         #10us;
         `uvm_info(get_name(), "Done env", UVM_LOW);
         phase.drop_objection(this);
       endtask : run_phase

    endclass

    program tb_run;

    initial
    begin
       tb_env env = new("env");

       // Requirement: Disable assertion env.ASRT with system call $assertoff(...)

       fork
         run_test();
         begin
          #5us;
          env.exp_val = 1;
         end
       join
    end

    endprogram

Solution

  • Yes you can use $assertoff for your purpose.

    Here is your code without $assertoff.

    class tb_env;
      int exp_val = 0;
      int act_val = 0;
    
      virtual task run_phase ();
        #10;
        ASRT: assert ( exp_val == act_val) else
          $error("Error");
      endtask : run_phase
    endclass
    
    program tb_run;
      tb_env env = new();
    
      initial
      begin      
         // $assertoff(0, env.run_phase.ASRT);
    
         fork
           env.run_phase();
           begin
             #5;
             env.exp_val = 1;
             $display("@%0t : exp_val - %0b, act_val - %0b", $time(), env.exp_val, env.act_val);
           end
         join
      end
    endprogram
    
    // Output -
    @5 : exp_val - 1, act_val - 0
    "a.sv", 7: $unit::\tb_env::run_phase .ASRT: started at 10s failed at 10s
            Offending '(this.exp_val == this.act_val)'
    Error: "a.sv", 7: $unit.tb_env::run_phase.ASRT: at time 10
    Error
    $finish at simulation time                   10
    

    And here is your code with $assertoff.

    class tb_env;
      int exp_val = 0;
      int act_val = 0;
    
      virtual task run_phase ();
        #10;
        ASRT: assert ( exp_val == act_val) else
          $error("Error");
      endtask : run_phase
    endclass
    
    program tb_run;
      tb_env env = new();
    
      initial
      begin
         $assertoff(0, env.run_phase.ASRT);
    
         fork
           env.run_phase();
           begin
             #5;
             env.exp_val = 1;
             $display("@%0t : exp_val - %0b, act_val - %0b", $time(), env.exp_val, env.act_val);
           end
         join
      end
    endprogram
    
    // Output -
    Stopping new assertion attempts at time 0s: level = 0 arg = $unit::\tb_env::run_phase .ASRT (from inst tb_run (a.sv:17))
    @5 : exp_val - 1, act_val - 0
    $finish at simulation time                   10