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system-verilog

Does the following code contain a race condition?

task SomeTask();
   bit a = 0;
   bit b = 1;
   fork
      if (a) $display("FOO");
      if (b) $display("ZIG");
   join_any
   disable fork;
   $display("BAR");
endtask : SomeTask

In VCS, this will seemingly always display BAR. However, going through chapter 4 and section 9.3 of IEEE-1800.2017, I am not able to ascertain that this code does contain a race condition as I suspect it does. My question is: how can one know from the standard whether or not this code contains a race condition?

Solution

  • It is a race condition because of these sentences in section 4.7 Nondeterminism:

    One source of nondeterminism is the fact that active events can be taken off the Active or Reactive event region and processed in any order. Another source of nondeterminism is that statements without time control constructs in procedural blocks do not have to be executed as one event.

    Your example has three processes. The parent process executing the fork and the two child processes for the two if statements inside it. The statements inside a fork can be executed in any order. If the second if(b) statement gets chosen first. "ZIG" gets displayed as seen by other tools on https:www.EDAPlayground.com. It's also possible that even if the first if(a) statement gets chosen first, there could be a switch to the other process before executing the disable fork.