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system-veriloguvm

If I use a blocking expression in the covergroup, do I need a sample directive from the previous code?


A covergroup is triggered from a sample directive from procedural code such as .sample() and from a blocking expression within a covergroup such as @(clk) or @(signal).

If I implement a blocking expression in the covergroup, do I need a sample directive .sample()?

class func_cov extends uvm_subscriber #(seq_item);
  covergroup cg @(posedge clk);
    option.per_instance = 1; // Per instance coverage
    option.auto_bin_max = 256; // Set maximum number of bins
    option.type_option = UVM_UNSIGNED; // Set coverage type to unsigned
    option.weight = 1; // Set coverage weight
    // Add coverage points to the covergroup
    coverpoint req.addr {
      bins range[] = {0, 255, 512, 1023};
    }
    coverpoint req.data {
      bins data_range[] = {[0:255], [256:511], [512:767], [768:1023]};
    }
  endgroup

  function new(string name = "func_cov", uvm_component parent = null);
    super.new(name, parent);
  endfunction

  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    cg = new("cg", this);
  endfunction

  function void write(seq_item req);
    // Collect coverage data
    cg.sample();
  endfunction
endclass

Solution

  • If I implement a blocking expression in the covergroup, do I need a sample directive .sample()?

    No, you do not need to call the sample method. In your code, coverage is sampled at the coverage_event, which is @(posedge clk)

    Refer to IEEE Std 1800-2017, section 19.3 Defining the coverage model: covergroup.