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interfacesystem-verilog

How to declare virtual interface with params in the top module (in the testbench)?

I have the following parameterised interface:

interface axi_interface #(parameter DATA_SIZE = 0)
  (input bit ACLK, input bit ARESETn);
   //write address channel signals
   logic [3:0]  AWID; //
   logic [31:0] AWADDR;
   .....
   .....
endinterface

I try to declare this interface as a virtual interface in the top module (in the testbench):

module girobo2_tb_top;
   .....
   .....
   axi_interface #(.DATA_SIZE(63)) axi_vif(tb_axi_clk, axi_arstn);
   .....
   .....
endmodule

But, I got the following error when I run the simulation:

# ** Error: (vsim-7065) ../sv/girobo2_tb_top.sv(245): Illegal assignment to type 'virtual axi_interface' from type 'interface axi_interface #(.DATA_SIZE(63))': Vir. 'axi_interface' interface must be assigned a matching interface or virtual interface.
Solution

  • In order to assign a parameterised interface to a virtual interface, you need to parameterise the virtual interface, too, eg:

    virtual axi_interface #(.DATA_SIZE(63)) vif;

    https://www.edaplayground.com/x/3KvL

    You might like to watch this video tutorial, which I have just come across. You'll see one the other regular contributors here is acknowledged.