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system-verilog

Classes method execution and systemverilog regions


I want to know when does any class method be executed, is it in active region set or re-active region set. I'm Trying to understand more the time that the design receive the input values from the environment, when the driver toggles the interface signals, is this process happens in the active or re-active region, and also when the monitor samples the DUT signals is this process happens at active or re-active region.

I'm trying to understand the Scheduling semantic of system Verilog

giving this example what will be the value of b ?

module tb;
  int b;
  class cla;
    function void changeb(input int bdash);
      b = bdash;
    endfunction
  endclass
  cla clainst = new();
  initial begin
    clainst.changeb(23); // Executes in the Active region or Re-active region
    $display("b=%0d", b); // Prints b=23 or b = 0   
  end
endmodule

Solution

  • Class methods or any other task/function for that matter are not tied to any specific scheduling regions. Procedural processes are started by initial, always, continuous assignments, or assertion action blocks. Once started, calling a method does not change the region the process executes in. One caveat is you can suspend a process waiting for a signal to change, and that change may happen in a different region, but the process resumes in the same region it original started in.

    In your example, your process gets started by an initial block in a module, so the assignment to b executes and gets updated in the active region. The $display statement that follows it prints its new value 23. Had you used a nonblocking assignment to b, it would still have its old value 0 when printed.