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system-veriloguvm

One IMP_PORT connected to multiple EXPORTS

I am creating a scoreboard which has a single implication port. I want to connect multiple exports from a parent class to the same imp port of the scoreboard class I am writing. Essentially (in pseudo-code):

class parent_class extends uvm_scoreboard;

  uvm_analysis_export #(my_type) export0;
  uvm_analysis_export #(my_type) export1;
  uvm_analysis_export #(my_type) export2;
  uvm_analysis_export #(my_type) export3;

  my_scoreboard m_scb;

  function void connect_phase(uvm_phase phase);
    export0.connect(m_scb.my_imp);
    export1.connect(m_scb.my_imp);
    export2.connect(m_scb.my_imp);
    export3.connect(m_scb.my_imp);

  endfunction
endclass

class my_scoreboard extends uvm_scoreboard;

  uvm_analysis_imp#(my_type) my_imp;

  function void write (my_type);
    // do something here
  endfunction

endclass

This works fine but I am wondering now, if we get 2 or 3 or 4 transactions broadcasted from their ports on the same clock cycle, will the write function be called twice/thrice/4times? This is the behaviour I would want.

I don't have a dependency on the order in which they are called but don't want to miss a broadcast because of my setup.

Solution

  • Yes, you can have multiple write()s called in an indeterminate order. If the scoreboard needs to know which port it came from, you will have to put that information in the transaction.