I have a sequence that needs to know when certain things have happened in the DUT to decide when to send the next item in the sequence, and I'm trying to find the best way to get that information to the sequence. I wanted to connect an analysis_port to the sequence since my testbench already has an analysis_port with the information I need, but my understanding is that analysis_ports need to be connected in the connect_phase, but uvm_sequence doesn't have a connect_phase. So is there anyway to connect an analysis_port to a uvm sequence? Or is there any other way to get the information from an analysis_port to a sequence?
My use case is the following: I am verifying a write-through cache and writing a sequence that sends some stores to the input of the cache. Due to ordering requirements of the DUT and the intention of this sequence, this sequence needs to wait until each store is seen on the output of the cache (written-through) before sending the next one.
You mean an analysis_export or analysis_imp...
How about doing this: extend your uvm_sequenceR and add the analysis_imp to that and implement a write function there. The write function needs to store the received information somehow, eg by writing it to a queue (which would also be a data member of your extended sequencer class).
Your sequence can then access that store easily, because it can get easily get a pointer to the sequencer using p_sequencer or get_sequencer().