Intertwine 0s betweeen bits SystemVerilog

Question

I want to intertwine 0s between the bits of a variable. For example, imagine I have a variable a as follows

a = 1101

Then, I want to obtain the following result

b = 1_000000_1_000000_0_000000_1

That results from intertwining 6 0s betwen each bit of a. I was wondering if there was any elegant way of doing this in SystemVerilog. Any help is appreciated.

Answer 1

b = 0;
foreach (a[i]) b[i*7] = a[i];