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system-veriloguvm

Same sequence to multiple sequencers in UVM

I have a DUT with 2 Interfaces of the same type. I have created 2 agents to drive the two interfaces. My idea is to drive the same signals on the interface ports to test a specific scenario. Hence, I thought of creating a sequence and driving it to the two sequencers of the agents. But I get an error. The code is something as follows:

my_sequencer m_seqr[2];
my_sequence m_seq;

for(int i=0; i<2; i++) begin
  fork
    int idx = i;
      m_seq.start(p_sequencer.m_seqr[i];
  join_none
end

I haven't shown the complete code for keeping the post short. I think my declarations and initializations are correct because I have a similar test with 2 sequences feeding into 2 sequencers working correctly.

My question is how can I achieve my objective of driving the same sequence into 2 or more sequencers?

Error is as follows(Haven't added the complete line of error):

uvm_test_top.m_env.m_my_agent_env.m_my_agent[1].m_seqr@@m_in_seq%0d[SEQ_NOT_DONE] Sequuence .... already started
Solution

  • You need to construct a new object for each sequence you want to start. Also, you need to reference [idx] not [i].

    my_sequencer m_seqr[2];
...
for(int i=0; i<2; i++) 
  fork
    int idx = i;
    my_sequence m_seq = my_sequence::type_id::create(...);
    
    m_seq.start(p_sequencer.m_seqr[idx];

  join_none