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system-veriloguvm

What is a virtual accessor?


This phrase is from "uvm users guide 1.1" page 20:

"In SystemVerilog, an important use model is to add randomization constraints to a transaction type. This is most often done with inheritance—take a derived object and add constraints to a base class. These constraints can further be modified or extended by deriving a new class, and so on. To support this use model, the accessor functions are virtual, and the members are protected and not local."

What is an accessor ? and why it has to be virtual?


Solution

  • Accessor means a get_* function, that simply returns a value, without changing the object's state. The value returned could be a member variable or it could be a more complicated expression depending on member variables. An example would be a point class, which can deliver coordinates in both cartesian and polar (https://en.wikipedia.org/wiki/Polar_coordinate_system):

    class point;
    
      local int x;
      local int y;
    
      // Accessor for x coordinate, cartesian
      function int get_x();
        return x;
      endfunction
    
      // Accessor for r coordinate, polar
      function int get_r();
        return sqrt(x**2 + y**2);
      endfunction
    
      // accessors would also exist for y and phi
    
    endclass
    

    If a function is virtual it can be overridden in a sub-class.

    Why it's important for the accessors you mention to be virtual is not apparent from your question.