I have been studying Verilog with Altera's Quartus II in combination with the terASIC DE10 board, but now something unexpected is happening.
For the sake of debugging, I am driving an LED through a switch, and between the two, I have inserted a module: switch-module-led
The module code is as below, where the value of the variable to_led
is updated every time in_clock_counter[0]
change.
module in_out (
input [31:0] in_clock_counter,
input from_switch,
output reg to_led
);
always @ (posedge in_clock_counter)
begin
if (from_switch)
to_led <= 1'b1;
else
to_led <= 1'b0;
end
endmodule
I would expect that if I press the switch, the LED would be lit. But, this is not the case. Using Simulation Waveform Editor I can see that the LED value changes. What am I doing wrong?
and the system works as intended
Happy you got it working.
isn't it a PLL block necessary to create a constant clock frequency? I thought so.
No, the best, most stable clock is the one that come straight from your oscillator.
The PLL allows you to make different frequencies from that clock (other then the usual: divide-by-2, divide-by-3 etc.)
For example, some allow you to make something as weird as a 23/3 times clock. Thus also a higher frequency. (In fact that is where the 3GHz processors get their clock from.) But the jitter specs will always be worse then your crystal.
But still that code should work from the PLL clock so I suspect something else is still wrong. I suggest you have a look at the synthesized netlist (schematic). And check what is all connected where.