Compiling verilog packages with same name

Question

Verilog 2K has support for compiling modules with different implementation using the "config" facility. In my multi chip uvm env I need to use 2 different packages(chip_top_pkg.sv) which have exactly the same name but different uvm components.

Is there a way to compile them separately and use them at elaboration. Or do I necessarily have to prefix all package names with say unique chip name?

-sanjeev

Answer 1

Unfortunately, SystemVerilog packages are used early in the compilation process and must be declared before they can be referenced. Module elaboration happens much later in the process, which allows later bindings for the config construct.

So your package names must be unique across the system.