When do we use "typedef class xxxxx" in uvm?

I'm not familiar with uvm, but trying to understand and studying.

I found the below code when I leaning the UVM.

typedef class driver; 
typedef class monitor;   

class env; driver d0; 
monitor mon0;   
function init_drvr (); 
d0 = new (); // initialize endfunction   
function init_mon (); 
mon0 = new (); // initialize endfunction endclass
endfunction
endclass

Especially

typedef class driver; 
typedef class monitor;

Probably it seems like declare something, but why those typedef is in there?

Would you please let me know why do we use

typedef class driver; 

typedef class monitor;

and how to understand this grammar?

Solution

It is rare that you would need typedef class name in SystemVerilog. Most programming languages require that identifiers used as type names be declared before they can be referenced syntactically. One place that occurs is if you have cyclical class references

class X;
  Y has_a_Y;
endclass
class Y;
  X has_a_X;
endclass

In order to compile the code for class X, class Y must be declared. If you change the compile order of the classes, then X becomes unknown. So we use what is called a forward typedef

typedef class Y;
class X;
  Y has_a_Y;
endclass

Now class X compiles as long as class Y gets defined before closing the current scope.

However, the UVM strongly discourages this kind of coding as these dependencies make the code less reusable.

Sometimes people use a forward typedef even when there are no cyclical dependencies because they are too lazy to compile their code in the correct dependency order.