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system-veriloguvm

How to use 2 different instances of the same class intest?


I have the following run_phase task in one of my test:

   //run_phase
   task run_phase(uvm_phase phase);
      tx_big_sml_diff_sequence tx_seq_i;
      axi_config_reg_sequence axi_seq_i;
      phase.raise_objection(.obj(this));
      for (int i = 2; i <= 9; i++) begin
                tx_seq_i = tx_big_sml_diff_sequence::type_id::create(.name("tx_seq_i"), .contxt(get_full_name()));
                axi_seq_i = axi_config_reg_sequence::type_id::create(.name("axi_seq_i"), .contxt(get_full_name()));
                axi_seq_i.transfers[0] = i;
                axi_seq_i.addr = `TX_FE_LIN_INT_ADDR;
                fork
                    begin
                       tx_seq_i.start(grb_env_i.tx_lin_int_agent_i.tx_lin_int_sequencer);   
                    end
                    begin
                       axi_seq_i.start(grb_env_i.axi_agent_i.axi_sequencer);
                    end
                join
      end
      phase.drop_objection(.obj(this));
      super.run_phase(phase);
   endtask // run_phase

Where axi_config_reg_sequence is sequence which is responsible for config specific reg (according to given address).

I want to config another reg beside TX_FE_LIN_INT_ADDR, how can I use the same sequence for config another?


Solution

  • You are not providing any details about the axi_config_reg_sequence implementation, so I am going to assume that the addr variable automatically takes care of configuring a register at that particular address. If that is the case, you can instantiate the same sequence one more time and then start it on the same sequencer as seen below:

              tx_seq_i = tx_big_sml_diff_sequence::type_id::create(.name("tx_seq_i"), .contxt(get_full_name()));
              axi_seq1_i = axi_config_reg_sequence::type_id::create(.name("axi_seq1_i"), .contxt(get_full_name()));
              axi_seq2_i = axi_config_reg_sequence::type_id::create(.name("axi_seq2_i"), .contxt(get_full_name()));
    
              axi_seq1_i.transfers[0] = i;
              axi_seq1_i.addr = `TX_FE_LIN_INT_ADDR;
    
              axi_seq2_i.transfers[0] = `SET_THIS_VARIABLE_AS_NEEDED;
              axi_seq2_i.addr = `YOUR_OTHER_ADDRESS_GOES_HERE;
    
              fork
                  begin
                     tx_seq_i.start(grb_env_i.tx_lin_int_agent_i.tx_lin_int_sequencer);   
                  end
                  begin
                     axi_seq1_i.start(grb_env_i.axi_agent_i.axi_sequencer);
                     axi_seq2_i.start(grb_env_i.axi_agent_i.axi_sequencer);
                  end
              join