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system-veriloguvmquestasimsystem-verilog-assertions

$past with an input signal

I want to verify that if an event occurrs, then at “num_ticks” in the past, some signal should have been asserted.

As an example, the property I wrote is:

property test_past;
  @(posedge clk)
    $rose(gnt) |-> $past(req, num_ticks);
endproperty

The problem here is with num_ticks. If num_ticks is an input signal to the module in which the property is written, then the assertion fails. If I declare num_ticks as an int, and assign it to a constant, it passes.

Does $past only work for constant values? This is not mentioned in the LRM.

I am using Questasim 10.3

Solution

  • You might use multiple assertions for this purpose.

    Suppose num_ticks is 4 bits wide, then you can do like this.

    genvar x;
generate
  for (x=0; x<16; x++)
  begin
    property test_past;
      @(posedge clk)
      (num_ticks == x) && $rose(gnt) |-> $past(req, x);
    endproperty
  end
endgenerate