SystemVerilog wait() statement

Question

Is the following code is supported in SystemVerilog?

int cnt = 0;
wait( cnt == (cnt+1) )

Could any one point me the section in LRM?

Answer 1

This is supported. But the main question is, what will you get by such wait statement, as this statement will never be evaluated as "true".

May be I can help you, if you provide more details on, what you exactly want to do through this wait statement.

Meanwhile, here is the code, as per your wait statement, with it's output. This will help you to understand, what this wait statement will do:

// Sample code, as per your wait statement
module top();
  int cnt;
  bit clk;

  always #5 clk = ~clk;

  always @ (posedge clk)
    cnt <= cnt + 1;

  initial
    begin
      $display("***** Before wait *****");
      wait(cnt == (cnt + 1))
      $display("***** After wait *****");
    end

  initial #100 $finish;
  initial $monitor("cnt - %0d", cnt);    
endmodule

// Output of this sample code
***** Before wait *****
cnt - 0
cnt - 1
cnt - 2
cnt - 3
cnt - 4
cnt - 5
cnt - 6
cnt - 7
cnt - 8
cnt - 9
cnt - 10
$finish called from file "testbench.sv", line 20.
$finish at simulation time                  100