Search code examples
system-veriloguvm

UVM RAL: Randomizing registers in a register model


I have a large register map modelled with RAL and I would like to randomize some of the registers. If I want to constrain the registers seperately then this is simple:

reg_model.register_a.randomize() with {value > 5;}
reg_model.register_b.randomize() with {value < 2;}
reg_model.update(status);

However, if I want a relationship between the two values written I think I have to add a constraint to the whole register model:

reg_model.randomize() with {register_a.value > register_b.value;}
reg_model.register_a.update(status);
reg_model.register_b.update(status);

The problem here is that the other 254 registers in the model will also get randomized. I could just update the two registers that I want randomized, but then the mirror will not match the hardware. If I had backdoor access working I could refresh the mirror, but I don't and I certainly don't want to read back 254 registers through the front door.

Is there a way to randomize just those two registers yet still have the constraint solver maintain a relationship between them?


Solution

  • You could do

    reg_model.randomize(register_a,register_b) with {register_a.value > register_b.value;}
    

    Then only registers a and b will get randomized.