Using typedef with wire in SystemVerilog

Question

When using typedef to declare a user-defined type, both these forms are accepted by EDA Playground:

typedef reg[4:0] reg5;
typedef logic[4:0] logic5;

However, if doing something similar based on wire type, then this format fails:

typedef wire[4:0] wire5;

I get "Syntax Error".

How can that be explained?

Answer 1

It is illegal to declare a typedef with a wire type, according to the IEEE Std 1800-2017. Refer to section 6.18 User-defined types:

type_declaration ::=                // from A.2.1.3 
typedef data_type type_identifier { variable_dimension } ;

A wire is not a data_type, whereas reg and logic are. A wire is a net_type.