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system-veriloguvm

event control "@" in systemverilog in uvm defined AFTER assignments

I'm trying to understand the UVM driver code defined in a "verificationguide.com" UVM env example : https://www.edaplayground.com/x/5r89

In the mem_driver.sv file, in the drive() task, the following code can be found : if(req.wr_en) begin // write operation DRIV_IF.wr_en <= req.wr_en; DRIV_IF.wdata <= req.wdata; @(posedge vif.DRIVER.clk); end

How is the event control @(posedge vif.DRIVER.clk); line written AFTER the events being controlled? Help me understand the intent of the developer in this case?

Solution

  • It's there to make sure wr_en is held active for at least one clock cycle before the next requested transaction. Otherwise the next transaction would immediately set it back to 0.