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system-veriloguvm

forcing internal DUT signal from UVM driver

I have a scenario. I have uvm_driver which has a virtual interface vif. This virtual interface has modports with signal a. There are two levels of simulation. lower level L1 and upper level L2. In L1, the agent is active and driver drives the signal a and in level L2, agent is passive as it is expected for DUT to drive this signal and only monitor is created. There is a temporary situation where the DUT to drive a is not yet ready and we need the driver to drive. Can you please tell me how to force this signal a(which is an internal signal now on level L2) from uvm_driver? I have complicated logic in my uvm_driver and wherever I am assinging a with vif, I want to force this signal a when I am in level L2.

Thanks in advance

Solution

  • UVM provides a method to overdrive signals, for example:

    uvm_hdl_force
uvm_hdl_deposit
uvm_hdl_force_time

    So, you can do something like this:

    uvm_hdl_force("my_tb.my_dut.a", 1'b1);