Verilog module in Xilinx "signal never used" error

Question

I have a Verilog program where I have to model an ALU that can add, subtract, check for equality and divide by 2. My code:

module alu(
input wire [7:0] sw,
 output reg [2:0] s, 
 output reg cout
 );

reg co1, co2;

always @(*) begin 

    if(~sw[6] & ~sw[7]) begin 
    s[0] = sw[0] ^ sw[3] ^ 1'b0; 
    co1 = (sw[3] & 1'b0) | (sw[0] & 1'b0) | (sw[0] & sw[3]);

    s[1] = sw[1] ^ sw[4] ^ co1; 
    co2 = (sw[4] & co1) | (sw[1] & co1) | (sw[1] & sw[4]);

    s[2] = sw[2] ^ sw[5] ^ co2; 
    cout = (sw[5] & co2) | (sw[2] & co2) | (sw[2] & sw[5]);
    end

    else if(sw[6] & ~sw[7]) begin
    s[0] = sw[0] ^ ~sw[3] ^ 1'b1; 
    co1 = (~sw[3] & 1'b1) | (sw[0] & 1'b1) | (sw[0] & ~sw[3]);

    s[1] = sw[1] ^ ~sw[4] ^ co1; 
    co2 = (~sw[4] & co1) | (sw[1] & co1) | (sw[1] & ~sw[4]);

    s[2] = sw[2] ^ ~sw[5] ^ co2; 
    cout = (~sw[5] & co2) | (sw[2] & co2) | (sw[2] & ~sw[5]);

    end
        \\more code
end

endmodule

I am getting this warning for 'co1' and 'co2'

signal is assigned but never used. This unconnected signal will be trimmed during the optimization process.

I am confused with the warning because from my understanding 'co1' and 'co2' are used to assign something. Overall when I run it on my board I get no outputs at all.

Answer 1

So this ended up being a non-issue. They were removed after synthesis.