Importing systemverilog package as another name

Question

Is there a mechanism to import a systemverilog package as another name, similar to what is available in Python?

I have a package I need to import, and the name of the package is top_pkg. I want to import it as subsystem_pkg

Answer 1

There is a a mechanism, but it is not easy for this purpose. What you can do is create a subsystem_pkg that imports top_pkg. Then you can export all the symbols imported from top_pkg so they will appear as if they were directly declared inside subsystem_pkg Normally, only those symbols declared inside a package are what are available to import, not what the package has imported (sometimes called a chaining of imports). The export command chains the imports.

What makes this difficult for this purpose is the way wildcarding works for import and exports. Every symbol you want chained has to explicitly appear in the chaining package. For example

package top_pkg;
  int a,b,c,d;
endpackage
package subsystem;
  import top_pkg::*;
  import top_pkg::b;
  export top_pkg::*;
  export top_pkg::c;
  int e = d;
endpackage

The first import statement say make all symbols in top_pkg candidates for importation; it doesn't actually import anything. The second import statement explicitly imports b. The first export statement says to export any symbol that was imported from top_pkg, which at this point is only b. The second export statement implicitly imports, then explicitly exports c. The last statement causes an implicit import of d, as well as an implicit export 'd'.

So when you import subsystem_pkg, you get symbols b,c and d from top_pkg as well as the locally declared `e.